Memory arrays on integrated circuits may be tested using different test mechanisms. One such mechanism is a memory built-in self-test (MBIST). Memory testing using this mechanism is implemented with a controller that is coupled to the memory array (or arrays) to be tested. The controller may generate various types of test patterns in which data is written to and read from the memory, wherein the reading of data may be used to verify whether or not the memory passes a given test. The controller may convey signals to the memory over address lines, data lines, and control lines (e.g., read enable, write enable, bank enable), and may receive signals over data lines as well. Thus, the controller may test the functionality of the entire memory array, including address and control circuitry, as well as testing individual memory cells. The controller may also provide signals to devices external to the integrated circuit in which the memory array is implemented in order to indicate the results of a particular test.
Scan testing is another mechanism that may be used in memory testing. Scan chains may be formed around the inputs and outputs of the memory array. Test input data may be shifted into the scan chain. After the shifting of input data is complete, one or more capture cycles are conducted to allow data to be written into and read from the memory array. The data read from the memory array (test output data) may then be shifted, via the scan chain, from the integrated circuit in which the memory array is implemented. The test output data may then be analyzed by a test system to determine whether the particular test passed or failed. In many cases, the speed at which scan testing of memory arrays is conducted may be significantly lower than the speed at which the integrated circuit is intended to operate.